1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having low voltage characteristic and advantageous integrity, and method for fabricating the same.
2. Description of the Related Art
Due to the fast development in semiconductor device industry such as high integration, fast speed and low voltage, a semiconductor device using the SOI substrate instead of a silicon substrate made of bulk silicon, has been proposed. The SOI substrate has a stack structure comprising a base layer as a means for supporting, a buried oxide layer disposed on the base layer, and a semiconductor layer disposed on the buried oxide layer and providing an active region.
Compared to general semiconductor device integrated on a silicon substrate, the semiconductor device integrated on the SOI substrate (hereinafter xe2x80x9cSOI devicexe2x80x9d) has advantages such as a high speed due to lower junction capacitance, and a reduction in driving voltage due to lower threshold voltage and latch-up prevention due to the complete isolation.
In the meantime, as the demand of portable electric products increases, it is required a reduction not only in the device size but also in the voltage supplied thereto. Currently, a method for lowering the threshold voltage of the transistor is frequently used so as to obtain the low-voltage device. There have been suggested those method for lowering the threshold voltage such as a structure in which two transistors are provided at one device. Herein, those two transistors consist of a main transistor and an auxiliary transistor being connected to the main transistor.
When the low-voltage device is embodied on the silicon substrate with above described structure, there is however occurred limitations such as an increase in the leakage current simultaneously although the threshold voltage is reduced. On the other hand, when the low-voltage device is embodied on the SOI substrate, since the SOI device has basically characteristics of low threshold voltage and low leakage current, the SOI device is probably suitable for manufacturing process of the portable electronics products requiring small size and low voltage rather than the semiconductor device embodied on the silicon substrate.
However, the low-voltage device having two transistors as above also incurs limitation in view of integrity since active regions for the respective transistors should be provided.
Accordingly, it is one object of the present invention to provide a semiconductor device having low voltage characteristic and advantageous integrity.
Further, it is another embodiment of the present invention to provides a method for fabricating said semiconductor device.
To accomplish foregoing objects, the present invention provides a semiconductor device comprising: a silicon-on-insulator (SOI) substrate of a stack structure comprising a base layer as a means for supporting, a buried oxide layer, and a semiconductor layer providing an active region; and a first transistor and a second transistor formed on the active region of the SOI substrate, wherein the first and second transistors are formed as a stack structure on one active region and they share one gate electrode, a drain region of the second transistor is electrically connected to the gate electrode and a source region of the second transistor is electrically connected to the active region.
The present invention further provides a semiconductor device comprising: an SOI substrate of a stack structure comprising a base layer as a means for supporting, a buried oxide layer, and a semiconductor layer providing an active region; a first transistor formed on the active region of the semiconductor layer, and comprising a gate electrode having a first gate oxide layer, source and drain regions formed in the semiconductor layer at both sides of the gate electrode respectively; a second transistor sharing the gate electrode with the first transistor, and comprising a second gate oxide layer formed on the gate electrode, source and drain regions formed on the second gate oxide layer; an intermediate insulating layer formed on the SOI substrate to cover the first and second transistors; source and drain electrodes being contacted with the source and drain regions of the first transistor respectively; a first metal wiring for electrically connecting the gate electrode and the drain region of the second transistor; and a second metal wiring for electrically connecting the active region of the first transistor and the source region of the second transistor.
The present invention provides a method for fabricating a semiconductor device comprising the steps of: providing an SOI substrate of a stack structure comprising a base layer as a means for supporting, a buried oxide layer, and a semiconductor layer providing an active region; forming a first oxide layer, a first conduction layer, a second oxide layer and a second conduction layer on the semiconductor layer successively; forming a conduction layer pattern, a second gate oxide layer, a gate electrode and a first gate oxide layer on the active region of the semiconductor layer by patterning the first oxide layer, the first conduction layer, the second oxide layer and the second conduction layer; forming first source and drain regions in the semiconductor layer at both sides of the gate electrode, and second source and drain regions at both ends of the conduction layer pattern, wherein a first transistor comprises the gate electrode, the first source and drain regions, and a second transistor comprises the gate electrode, the second source and drain regions; forming an intermediate insulating layer on a resultant; etching-back the intermediate insulating layer until the second source and drain regions of the second transistor are exposed; forming a first contact hole and a second contact hole exposing the first source and drain regions of the first transistor respectively, and a third contact hole and a fourth contact hole exposing the gate electrode and the active region respectively by selectively etching selected portions of the intermediate insulating layer; forming a metal layer on the intermediate insulating layer with a sufficient thickness to fill the first, second, third and fourth contact holes entirely; and forming source and drain electrodes being contacted with the first source and drain regions of the first transistor through the first and second contact holes respectively, a first metal wiring for electrically connecting the gate electrode and the drain region of the second transistor through the third contact hole, and a second metal wiring for electrically connecting the active region and the second source region of the second transistor through the fourth contact hole on the intermediate insulating layer by patterning the metal layer.